Cache memories are prevalent in data processing systems. Two common cache organizational structures are known as fully associative cache arrays and set associative arrays. Set associative caches have a number of sets, indexed by an address value, where each set contains a number of storage locations commonly referred to as “ways”. One way of a particular set is selected each time a cache line is addressed.
Various conventional caches permit the locking of ways of a set associative cache. When locked, cache lines within a way cannot be replaced or written with a new tag value. Locking mechanisms provide an inexpensive mechanism to ensure that critical information, either instructions or data, is always accessed from the cache, which is faster than addressing system memory. Information is preloaded into a specified way for each cache set and then locked to prevent future replacement. Therefore, the number of long latency cache misses can be minimized with the use of selective locking of cache ways. The locking of ways in a set associative cache however must be used carefully to avoid severely restricting use of cache memory for the execution of applications.
When set associative caches are desired to have data stored or written, there is often an operating condition wherein the desired address associated with the data is not present in the cache. Conventional set associative caches have replacement circuitry that functions to determine what existing address to overwrite the new data with. The maintenance and overhead associated with this functionality adds additional expense to a data processor and typically delays operation of the set associative cache.
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